The I/O Channel Design And Access Mechanism Research On FPGA-based Dual-core UCard

Dual-core UCard(Universal Smart Card) is a new type security architecture of smart card, it can store more than one COS and its applications. It adopts the idea of complete isolation among the COSs to ensure the storage and access security.I/O Channel is used for serial data transfer between Dual-core UCard and terminal device. The data transmission function of I/O Channel can be divided, following moduling and layering theory, into three layers: physical layer, data link layer and application layer. A serial communication interface is used to accomplish physical layer and data link layer function, and an 8051 microcontroller core is responsible for application layer data transmission.UCard serial communication interface has one internal clock source and two I/O ports. Serial communication interface mainly consists of baud rate generator, transmitter module, receiver module and FIFO module. Baud rate generator can produces 16 times the baud rate clock for the receiver to achieve sampling judgement. A internal finite state machine controls the parallel–to-serial data transmitting process of transmitter module. The start bit, parity bit and stop bit are automatic added without user intervention. Receiver module uses another finite state machine to detect start and end of character frame from the serial bit stream, it also extracts 8 bits parallel data from the bit stream as output. When a data transfer is done, the serial communication interface issues a interrupt request to the microcontroller core. The FIFO module reduces the frequency of interrupt requests, and the overall system performance is improved.The research on access mechanism makes dual-core UCard seamless access to the existing smart card terminal equipment. Scheduling module and I/O channel multiplexing module are two key components of access mechanism hardware platform. The scheduling module controls the operation of the two microcontroller core in dual-core UCard by starting or stopping their clock signals. A state control logic assures the mutually exclusive operation of two cores. I/O channel multiplexing module realizes time division multiplexing access to the serial interface from the two microcontroller cores.ModelSim is ultilized to simulate the hardware design of I/O channel and access mechanism functionally. The design is verified on FPGA platform as a whole.