Design And Optimization Of Memory Cell Structure Of Chalcogenide-Based Phase-Change RAM

Chalcogenide random access memory(CRAM) makes use of the thermal effect of the current pulse to make its storage material—chalcogenide has a reversible structural phase change between amorphous and polycrystalline states which has great difference in resistance values(usually 3～5 magnitudes) to store and read data.CRAM has high recording density,high-speed programming,high cycle count,low power and simple craft technology.CRAM has demonstrated a possibility as a promising memory technology.The most important issue in CRM's research is reducing writing current,which is too high to be compatible with the present COMS technology.What's more,lots of heat energy will be produced during CRAM's work,which may bring negative effect to CMOS.Therefore,the compatibility between CRAM cell and CMOS is a constraint in the process of CRAM's development.According to the working principle and the characteristic of CRAM,This work starts from the heat conduction model,using the numerical analysis to simulate and analysis the thermal field distribution and its evolvement,emphasizely seeing about the effect caused by the heat from the CRAM memory cell to CMOS and the phase change volume of the storing material.A newly CRAM cell structure has been designed which has realized the thermal compatibility between CRAM memory cell and CMOS.As GST has a good performance in heat insulation,a GST layer is inserted between bottom electrode and the heat layer in the traditional CRAM cell structure to prevent heat diffusion from heat layer to bottom electrode,which is helpful to the thermal compatibility between CRAM memory cell and CMOS.What's more,two GST layers can take phase-change in the same time,which can promote the utilization of the heat energy to reduce writing current.The writing current has been observably reduced and the low power has been realized by the device optimization.The optimal size of each layer has been obtained by analyzing the influence of the size of each material to the writing current and finding the optimal cell resistance through circuit simulation.Finally,the reset current has been reduced to 0.36mA under the CRAM cell structure with such materials' size. 0.36mA is lower than all the reset current value which has been publicized.Therefore, the electrical compatibility between CRAM and CMOS and low power have been well realized.The newly-style CRAM cell designed in this paper through thermal analysis and device optimization has well realized the thermal compatibility between CRAM memory cell and CMOS,and the reset current has been reduced to 0.36mA,which decreased the power greatly.In conclusion,the studies of this dissertation reach the anticipate targets with some innovation and integrity,and can impel CRAM to develop toward the product.