The Design Of Testbench For Network Processor

Traditional test-bench is mainly applied to the functional verification of chips. A traffic model-based testbench for the verification of network processor is introduced in this paper. By means of traffic model, processing performance of the designed chip can be analyzed during verification, so the performance design of the chip can be judged.The application of advanced verification methodology can accelerate the development of testbench for network processor, while the application of traffic model make it possible that performance analysis of the network processor can be realized just by software simulation instead of high-end hardware equipments.By analyzing the verification requirements of the network processor, advanced verification methodology is adopted to design the basic structure of the testbench for network processor. The mathematical principles and realization progress of poisson model, M/M/1/K queuing model and M/G/1 queuing model are introduced; Virtual external memory model and graphic user interface are designed to increase the efficiency of the verification. Simulation results show that the testbench sufficiently meets the need for functional verification of the project. Meanwhile, after the application of M/M/1/K model and other traffic models, performance metrics analysis results also meet practical application demand.