Research On Verification Methods Of Communication Chip

Chip verification plays a key part to increase the ratio of taping-out successfully. Some data indicate that the major reason why the ratio of taping-out successfully one-time is below 50% is that function verification is not well done. According to verified objects in different areas and verified modules in different levels, there are many function verification directions, such as CPU, on-chip bus, memory and so on. So making verification strategies and methods according to investigated objects has a great guiding significance.Generally, communication chips have these functions: frame exchange, re-transmission, channel competition, back off and so on. Based on these characters, test cases must be designed by simulating network environment in the function verification. Not only the chip processing conditions after getting channel competition but also the complicated conditions of multi-station competition are contained in the verification. On these requirements, periods of verification method are presented in this thesis. White box verification method with single direction test cases is taken in the first period. Multi-station network environment is simulated in the second period. Test cases imitating transmitting under multi-station competition are added. The next transaction is triggered by the results which generated by the stations. Half automation is implemented by self-triggered circularly.At present, abstraction, automation, reusability and easying to formal verification are the verification techniques' goals. In this thesis, research on communication chips' verification methods starts from these aspects too. Multi-level hierarchy is built in the verification, interface pins are packaged and functions are abstracted into transaction level. Test cases are generated by the random number generator with constraints, which increases the automation of verification. Each module in the verification hierarchy is function-independent. It is easy to be reused into other communication chips' verification or next generation products' verification. Verification modules are described by System Verilog, and protocol properties and requirements are verified by assertions, which can realize formal verification partially. Finally, structure coverage and function coverage are combined to analyze the verification, which can make verification meet the engineering requirements.