Research On The Decoding Algorithms And Hardware Implementation Techniques For Generalized Iteratively Decodable Codes

Currently, turbo codes and LDPC codes are regarded as two most advanced and powerful channel coding methods, which can surprisingly approach to the ultimate Shannon limits by their unique ways due to the effective use of the iterative decoding algorithms. In this thesis we perform the extensive studies on the turbo codes and the LDPC codes, respectively, from theory to hardware applications.First, this thesis introduces the basic principles of LDPC codes, including the fundamental concepts, the codes description, the encoding methods and the decoding algorithms, respectively. The performance simulations are carried out over an AWGN channel. The method used to construct irregular LDPC codes in this thesis is based on a generator matrix so as to reduce encoding complexity. Meanwhile, we study the Log_BP and BP_based reduced-complexity decoding algorithms. Second, we investiagte the principles of turbo codes, including the encoding method and normal decoding algorithms, and perform the numerical simulations over the AWGN channel. The author presents two new methods for the design of the so-called"simile old-even symmetric"interleaver since it is one of the most important factors that impact the error performance of turbo codes.The FPGA design and implementation of turbo codes is given in detail. First, we analyze the structure of parallel decoder and the serial decoder, respectively. Then, we employ one serial artichitecture with one forward recursion unit and two backward recursion units. The decoder memory can be reduced at the cost of a modest decreasing in the processing speed. The author makes some improvement to MAX_Log_MAP algorithm based on this decoder architecture. Then, we determine the main parameters of turbo codes for the realization of hardware process. Based on the theory, we use the idea of top-down design to program the encoder and decoder with Verilog HDL. Moreover, we synthexize and analyze the static time of the design with ISE and ModelSim to verify the correctness of our approach. The simulation results show that it is feasible for the precept of using FPGA as the platform of the hardware implementation.Finally, the comparison between turbo codes and LDPC codes are made explicitly, and the inherit relations between the two iterative decoding algorithms are presented.