Design And Implementation Of Embedded Linux Audio Driver And A Simple Player

With the rapid development of computer technology, embedded audio system has been applied to all aspects of people's life and community, Embedded audio technology is widely used in automotive audio, 3G mobile phones, personal digital assistants (PDA), portable multimedia players (PMP) and so on.After studying the Samsung S3C2410 processor and UDA1341 codec,The purpose of this paper is to connect an embedded audio system with them using IIS audio bus , design of the the corresponding hardware connection and logic working frame, and prepare the device driver of the audio codec chip UDA1341TS.All of these are done for implementing playing and rewording of sound. On this basis, achieve a simple player application to verity the driver functions's design and implement are correct.Considering the conditions of laboratory equipment, selected UP-NETARM2410-S development platform laboratory equipment provided by BoChuang company for development working. UP-NETARM2410-S development platform uses S3C2410 microprocessor CPU, audio codec chip UDA1341TS devices is included, and its peripheral equipment have a wealth expansion.S3C2410 microprocessor has a built-in IIS bus interface, you can directly connect the external UDA1341TS audio codec chip. S3C2410 processor and audio codec chip UDA1341TS are connected in two parts of hardware pins: one is the IIS bus pins for transmissing audio data; the other part is the L3-pins connection interface for controlling audio signals, such as the volume size.S3C2410 microprocessor uses ARM9 core, ARM chip with built-in IIS interface can read data from IIS bus,at the same time it can also provide data transmission/reception mode based on the DMA channel for the FIFO data, in order to achieve full-duplex mode. The chip uses two serial data lines as input and output lines. IIS data lines can receive and send audio data at the same time through the dual-channel DMA, so that sending and receiving data can both work in the same time.The output audio buffer is set of DMA channel 2, input audio buffer is set of DMA channel 1.Because IIS bus only deal with audio datas, so UDA1341TS chip provide IIS speaker and microphone interface, but also provide built-in L3-bus interface to control the transmission of the audio datas, L3 interface is equivalent to mixer control interface, through the L3 interface, S3C2410 processor can do a variety of settings to UDA1341TS, including the system frequency, power control, volume and so on.S3C2410 and UDA1341TS communicate with L3CLOCK, L3DATA, L3MODE pins.L3 interface trsmission timing is controlled by GPIO port programming, through the L3 interface, informations is divided into two modes, address mode and data mode. Address mode is used to determine the addresses of data transmission's purpose register through the L3 interface, data model is used to set the specific bits of the register to achieve the UDA1341TS chip initialization setting.Device driver application shieldes the details of the hardware, so that applications can operate the hardware device as ordinary documents. Each driver has a file_operations data structure, which include a series of function pointers, pointing to the developed interface. When the process using system calls such as read or write operations to access a equipment, the system finds the device driver through the corresponding major device number of device, and then read the data structure of the corresponding function pointer, give the controlling rights to the interface function, complete the call. Therefore, the preparation of a driver is to complete the file_operation structure's function pointers .In the designing process of the Audio equipment driver, DMA buffer memory management and designing are the most complex parts. Audio equipment needs high real-time requirements, so the reasonable using of memory can speed up the handling of audio data, and reduce the delay time. BDMA controllers of Samsung company have no built-in DMA storage area, the driver must allocate DMA buffers for the audio device. The sound datas which is need to be played or recorded can be loaded into the DMA buffer directly. In this paper, the whole cache will be divided into a number of data segment buffer. Such a large segment of the data processing is divided into several short paragraphs, After dealing with a segment buffer data, they can be sent through the DMA.UDA1341TS driver is composed of two parts, one is DSP devices for voice recording and playing, the other one is Mixer devices used to control sound, we need registering two device to the kernel. Developing driver is to complete the corresponding functions in accordance with the actual hardware.DSP driver implement: equipment opening function completes the inspection of equipment, such as the number of users, the way of opening and so on; equipment closing function completes the release of the buffer area and the closure of documents and equipments; Audio data writing function implements playing sound function, first copy user data to the kernel address space, and then create a DMA buffer, write data to the buffer, and then send data into DMA transfer queue, through channel 2 sending data in order to play sound; audio data reading function implements recording audio data, the process is similar to writing, but the direction of data transmission is opposite; audio data of the control function controlls of the voice sampling rate, stereo, channel selection and speeding and so on..The realization of Mixer drive is relatively simple, it mainly used to control audio mixing effects, there is no implementation of reading or writing operations. Finally,in the Qt/Embedded development environment, programing a simple player application,to test whether the driver development is correct or not.As a central issue of modern human visual perception study, embedded audio system will be research and development continue in-depth. Among the significance not only provides the feasibility of experimental basis for correlation theory, but more importantly, for a new try for new design, for the further research and application of future synchronization integration methods provide a viable and meaningful theory and practice basis.