The Design And Implement Of Discrete Cosine Transform With High Speed And Accuracy

In recent years, multimedia technology's booming growth creates a great demand for real time video compression in many fields. As the critical technology in spatial redundancy compression, how to make the search of Discrete Cosine Transform algorithms more effective, faster and nicety is always the key point of hybrid encoding based video coding standards.This article is dedicate to the hardware implementation of 2D FDCT/IDCT FPGA core for HDTV application.First, video coding standards, DCT's function and development are discussed in the paper. Then, DCT's mathematical theory, some commonly used fast algorithms and hardware realization are analyzed, and the drift phenomenon caused by IDCT error is discussed. Under IEEE standard 1180-1990, measuring IDCT transform precision with different DCT coefficients'multiples and intermediate bits, analyzing their effects on precision. In the end of the research, finishing 2D FDCT/IDCT design based on RCM structure, which is composed of multiplier based 1D FDCT/IDCT units and Ping-pang structure based transpose RAM; and finishing all the three FDCT and one IDCT's function verification, synthesis, timing verification, and FPGA verification under the Altera's Cyclone EP1C12Q240C8 FPGA. The results indicate that the design can run at 130 MHZ and meet the HDTV demand of MPEG-2 standard. The accutacy is better than IEEE standard 1180-1990.There are 4 one-dimension units designed in this thesis: 1D FDCT decomposition algorithm, W.H.Chen algorithm, Loeffler algorithm, and 1D IDCT W.H.Chen algorithm. Optimized Booth multiplier is used in FDCT decomposition algorithm design to increase the circuit speed, simplify the structure and minimize area. Propose an improved IDCT W.H.Chen algorithm, optimizing data stream in the multipliers, and using only 7 static coefficient multipliers to finish the design.