Design Of A High Performance Scalar Multiplier Of The ECC Algorithm Based On Binary Field

With the development of e-commerce,puts forward a higher demand for the speed of ECC.Scalar multiplication,as the vital element of elliptic cryptosystem,large data bit width lead multiple cyclic iterations,and data dependence brings long running time delay,it becomes the bottleneck of elliptic curve cryptography.The design and implementation of scalar multiplication scheduling algorithm and field operation unit becomes the key technologies.In the point operation layer,for the Lopez Dahab-Montgomery scalar multiplication algorithm with low resource utilization and long cycle iterations,a three-multiplier parallel Montgomery scalar multiplication algorithm is proposed.The algorithm improves the utilization of hardware resources by reorganizing the data flow diagram and improving the parallelism of modular multiplication,and reduces the cycle iterations of each cycle to half of the LD Montgomery algorithm.In this algorithm,the critical path delay is increased fromTMUL to TMUL+TSQR+TADD,but the Tsqr+TADD is far less than TNUL,therefore the algorithm can effectively improve the computational efficiency of elliptic curve cipher system.In the field computing layer,the hardware structure design of modular multiplication and modular inverse field unit is improved.Aiming at the problem of the critical path delay of the parallel high Significant digital modular multiplication unit,the critical path is shortened fromTADD+11TxoR to TADD+8TXOR by improving the packet bit width of the multiplier.Aiming at the SQR-ITA(Square-Itoh-Tsujii algorithm),the modular inverse unit needs to ?se the modular square operation for a long time,which can effectively reduce the cycle about 17%?34%.Based on the above scheme,a high performance scalar multiplier is designed for elliptic curve cryptosystem algorithm in the Binary field,which is based on the TSMC 180nm platform and Xilinx VIRTEX5 FPGA platform,and verify the results of the OpenSSL.Under the TSMC 180nm process,GF(2163)scalar multiplier hardware circuit area up to 3.5mm2,the frequency up to 100MHz,the speed up to 3.98?s,than the existing solution performance upgrade 26.3%-64.1%.Under Xilinx Virtex5 FPGA,the scalar multiplier of GF(2163)scalar multiplier consumption slices number of 24227,LUT number is 42410,the frequency up 87MHz,the speed up to 4.5?s,than the existing solution performance upgrade 11.7%?52.6%.