Design Of Acquisition-and-Storage Board In Radar Signal Processor

With the gradual maturity of the radar imaging technology, image resolution and data sample rates are becomming much higher. Hence, the radar imaging technology needs to store mass data. In order to accommodate the future development of the radar imaging technology, a high speed and large capacity data storage system is urgent to be designed. A high-performance AD chip, solid-state FLASH memory chips and FPGA (Field Programmable Gates Array) are used to realize high-speed data acquisition and real-time data storage for the system. A high-speed LINK port between data acquisition board and DSP board and a USB interface between data acquisition board and the host are exploited to finish the command and data transmission. Furthermore, in order to reduce the burden of the LINK port and achieve real-time radar imaging, some algorithms, such as DDC, RC, are realized through FPGA.In the paper a kind of structure of radar imaging signal processor is firstly given. Secondly, the hardware design of the system is discussed, and the corresponding softeware is designed. Thirdly, the development prospects of the data acquisition and storage board are briefly introduced. Lastly, a summary of the works is given.