Technique Research Of Power Line Frequency Hopping Communication Based On FPGA

Frequency hopping system's frequency bandwidth is wider than changeless frequency communication system. Its ability of anti-jamming and anti-capturing is stronger. CDMA, frequency bandwidth sharing and worknet construction can be realized in a frequency hopping system. Frequency hopping system is instantaneous narrow bandwidth communication system, so it is easy to be compatible with narrow bandwidth communication system.A PLC system based on FH technology is presented here. Because of the adoption of FH technology, the system can overcome high levels of interference and frequency selective fading. The system's bit error rate is lower. Function of multi-user is realizable. The system can adapt well to the power line channel that is seriously disturbed and declined.The interrelated theories of the FH system including its work theory, its system structure and its key technology are researched. The FH sequence based on m-sequence is designed. The design targets of the FH system are presented. The software and hardware design scheme are given.The system's hardware contains two modules: FPGA module and control module. FPGA module is available Xilinx Spartan-3 series XC3S400, so the system's hardware design is namely the design of the control module. The control module contains MCU, AD conversion circuit, DA conversion circuit, signal adjusting circuit, filtering coupling circuit and so on. Detailed discussion about transmiting and receiving filtering coupling circuit is presented. Because of the problem of power line's impedance matching, they are the most difficult section of the whole design.The system's software is realized on FPGA and ATmega16. Modulating logic design, demodulating logic design and bit synchronization design are fulfilled in FPGA. Direct digital synthesize technology is adopted in modulating logic design. Orthogonal NCO demodulator is adopted in demodulating logic design. The lead-lag-synchronization is adopted in bit synchronization logic design. The system protocol is realized on MCU. The data frame structure that is used during the receiver and transmitter's communication is designed. The flow chart of transmtting and receiving program are presented.Some waves about the system's modulating, demodulating and bit synchronization are collected in this paper. The bit error rate of the PLC system based on FH technology is tested based on 220V power line environment in the authors'laboratory. When the communication distance is about 100m, we didn't discover bit error. The anticipative communication objectives are achieved.