Design Of 6 Bit Flash Ultra Fast Speed ADC

As a special interface connects with analog and digital circuits, analog-to-digital converter(ADC) is the key device of advanced communication, radar, sonar and many consuming electronic products. With the science and technology rapid developing, the need for the performance of the ADC,especially the speed, become higher and higher. The performance of ADC even has become the key factor of the whole device performance.This paper aims at the design of the ultra high speed ADC, directing at the research of structure of flash ADC, especially paying attention to the research of speed and offset cancellation technique. I adopt a new technique to cancel offset voltage——chopping. This technique mainly bases on a set of random number generators(RNG) to exchange the inputs of comparator quickly and randomly, so that the offsets in the comparator inputs can be nearly zero on average. I designed a kind of RNG, which has an outstanding randomicity and can produce the random number at the speed of 1GHz sample/s. Considering the comparator is the key point for influencing the speed of ADC, I give the especial priority to the design of it. In addition, I also add the correction consideration in the digital encoding circuit.After simulating the circuit, the ADC proposed can be 1GHz sample/s. The maximum INL and DNL are 0.42LSB and 0.49LSB. When giving a sine wave with the frequency of 16.6MHz to the input, the SFDR can be 41dB. When adding a offset voltage of 10mV, the SFDR of the chopped ADC can be 3dB higher than that of the non-chopped ADC.The ADC's layout design is based on HJTC 0.18μm CMOS mixed signal process. I have completed the layout design of the main parts of the ADC.