A Design And Implementation Of SFN Adapter Based On DMB-T

With the advent of information age, the Analog TV system is destined to be replaced by the Digital TV system and hence Single Frequency Network (SFN) implementation of digital television terrestrial broadcasting becomes a hot topic of research. The key of SFN implementation resides in resolving the transmission synchronization problem of different broadcasters. This paper presents studies of a SFN Adapter based on the DMB-T standard, which is a key equipment to achieve the synchronization in DMB-T Single Frequency Network.A major function of the equipment is to insert Mega-frame Initialization Packet (MIP) into the transport stream so that each relay station can calculate the synchronized broadcasting schedule according to the time information included in the MIP. Moreover, it can set the traffic control parameters and broadcasts these control information with the MIP.An integral design of DMB-T SFN Adapter based on a FPGA and a single-chip is presented in this thesis. The whole system is divided to two parts according to their functions: the control panel and the processing board. A practical hardware platform design is accomplished through careful selection of various components and circuit schematic diagram design of each part. Based on the hardware design, a DMB-T SFN adapter software implementation is then presented.In the actual development process, problems focus on how to achieve conversion of ASI / SPI flow, how to handle communications between control panel and processing board, and how to realize construction and insertion of MIP, synchronization of stream, as well as adjustment of code flow rate. In this thesis, a series of solutions are proposed for these difficulties and the whole design is accomplished via functional modules, which improves the reusable merit of code and reduces the secondary development and upgrading costs. The paper also proposes a new PCR correction algorithm, which delivers the PCR difference through transport stream to avoid repeating search and positioning of PCR. The proposed method not only saves FIFO logic resources, but also avoids repeating read and write control of FIFO in storage of subtraction values. Moreover, the schedule control is relatively simple and the program is simplified. Online simulation results show that the design achieves the functional requirements of DMB-T SFN adapter. With the completion of practical equipment, this paper also presents the debugging results obtained from a special stream analyzer. Analyses of the observation results prove the feasibility and reliability of the design and demonstrate the achievement of expected technical indicators. Finally, this paper summarizes the contribution of the research and gives an outlook on future improvements on this design.