Research And Hardware Implementation Of Rate Control Algorithms For JPEG2000

JPEG2000 is a next generation still image compression standard, which is widely used because of its excellent compression properties. Rate control is a very important part in JPEG2000 encoding, which directly determines the whole coding efficiency and the quality of image compression. Therefore, it is very important to JPEG2000 hardware realization to reduce coding time and storage resources using high efficient rate control arithmetic.First, the main coding processes in JPEG2000 are introduced and the software realization of core coding and decoding arithmetic in this paper settled solid foundation for the realization of JPEG2000 rate control based on the reaearch group has completed the work.Second, a new rate control arithmetic is proposed in this paper based upon the analysis, the control precision is close to JPEG2000 standard, the coding efficiency and calculating redundancies are greatly improved, the number of coding passes reduced more than 90 percent based on very low code rate through software verification.Then, the VLSI structure of rate control system is designed according to the proposed algorithm, include designing hardware structure of key modules(including block bytes preallocation module,Tierl encoder module ,pass slope computing and adjusting module etc.) and writing Verilog code and the function simulation and timing simulation are finished.Finally, a software and hardware cooperative work verification system is designed for the FPGA verification. Tierl coding and rate control are hardware completed, wavelet transform, Tierl decoding, inverse wavelet transform and serial port transceiver etc are software completed. By comparing original image and reconstructed image of PSNR, the rate control effect is finally obtained.