2D Dynamic Patitionable Memory Based On Multicore Hardware

With the continuous improvement of integrated circuits and computer techniques, the multi-core architecture provides a powerful ability to enhance the overall performance of the current processors. However, memory developed relatively slower which imposes bottleneck on the computer performance. Therefore, how to improve the performance of in multi-core architecture emerges as a hotspot and multi-port memory correspondingly attract great attentions from the researchers.Multi-port memory provides multiple ports in a multi-core architecture, which facilitates each core's simultaneously access to memory. It is the key point of this paper on how to effectively use and address the multi-port memory while avoiding access conflicts in the multi-core system.This thesis designs a two-dimensional multi-port memory. It adopts a two-dimensional addressing method to change the address in both X and Y axis. The memory provides multiple ports to facilitate parallel access from different cores.Each dimension of the two-dimensional multi-port memory is addressed linearly, so when multiple cores access it simultaneously there will be access conflicts. This paper proposes to partition the entire two-dimensional multi-port memory to different banks statically or dynamically, and designs corresponding circuits for address-conversions.This thesis implements the design on Xilinx Virtex4 ML403 development board, and evaluates it with multi-core parallel programs. The result shows that under equal task workloads, the system reduces the clocks by 58.33%, and memory conflicts by 55.28%.To sum up, the two-dimensional multi-port memory combines the merits of two-dimensional addressing techniques and multiple ports, which facilitate the memory access operations and fully utilizes the agility of two-dimensional memory. Based on multi-core architecture it furthermore proposes partition mechanism to minimize the speed gap between the processor and memory, and improves the system performance.