Research On Carrier Recovery And System Implementation In FY-1 Receiving System

This paper mainly studies carrier recovery and system implementation in FY-1 receiving system. Presently, most of FY-1 receiving systems use analog or half-digital demodulations, which have some disadvantages, such as poor anti-noise performance, not conductive to system integration and upgrades. So, a new all-digital demodulation scheme which is easy for FPGA implementation is proposed in this paper. This demodulation scheme uses PCI bus for data storage which has higher storage rate and better compatibility with the current computer's motherboards than ISA bus commonly used in the present FY-1 receiving systems.Firstly, according to project requirements, an all-digital demodulation system scheme, based on which the classic self-synchronization algorithm of carrier recovery is simulated, is designed in this article. This paper focuses on discussing how the coefficients of loop filter Kp , Ki influence carrier recovery performance. Through simulation, the best filter coefficients will be applied to system simulation platform and system implementation. Secondly, system platform is built, and on the basis of completing system simulation to prove the feasibility of the demodulation scheme, the system hardware circuit is designed. Finally, the overall performances of this demodulation card, such as bit error rate, stability, reliability and operational satellites demodulation are respectively tested through using different data sources. The test results show that this all-digital demodulation system is feasible and the demodulation performance is good.