Font Size: a A A

Researching And Implementation On Carrier Recovery Algorithm Of DVB-S2 Demodulator

Posted on:2009-05-30Degree:MasterType:Thesis
Country:ChinaCandidate:Y H LiFull Text:PDF
GTID:2178360242994137Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
As the communication techniques improves, the satellite digital television system DVB-S will be replaced by the second generation standard DVB-S2. It is necessary to follow the newest communication techniques for the national digital television industry is behindhand.This paper works on the carrier recovery techniques of DVB-S. Carrier recovery is an important part of the demodulator of digital communication systems, and it is used to correct the frequency offset, phase offset and the phase noise caused by the transmission channel and the demodulation.Frequency offset, convergence time, phase noise and hardware cost are the most important factors for algorithm selecting. First, the carrier recovery loop is divided into two parts, frequency recovery loop and phase recovery loop. Frequency recovery loop is used to correct the initial frequency offset and phase recovery loop is used to correct the residual frequency offset and phase offset. Five classical algorithms are studied. Quadricorrector and Direct-Detector can capture small frequency offset range while Maximum-Likelihood and Differential-Power have complex hardware, so Pilot-aided detector is used in frequency recovery loop. And Polarity Costas Loop and Phase Offset Accumulation are adopted in phase recovery loop and lock detector respectively. C language is used to setup the float point model. Performance including frequency offset range, phase noise and convergence speed are simulated. It shows that at least 20 percents of symbol rate frequency offset can be captured, and the convergence speed is 50us when the frequency offset is 80kHz. The loop filter gain and the lock detector threshold are set according to the simulation result. The BER of the whole loop is also present. It's about 0.5dB worse than the theory. Fixed point model and RTL code are finished, and the hardware structure is also optimized. Finally, the FPGA synthesis shows that hardware's highest speed is 85MHz, while about 3000 LUTs are utilized.
Keywords/Search Tags:Carrier Recovery, DVB-S2, Frequency Detection, Phase Detection
PDF Full Text Request
Related items