Design Of Digital Correlating Demodulator Applied On Weak Signal Detection

With the development of modern science and technology, higher standards are required on detecting the signals, especially the weak signals. It becomes an important subject to measure the weak signals from strong background noise and obtain the accurate data under critical conditions.The Lock-in Amplifier, which is based on phase lock-in amplifying technology, is a specialized instrument detecting weak sinusoidal signals in the condition of strong background noise. However, there are many disadvantages of traditional analog LIA, such as temperature draft impact, poor immunity to interference, low measuring accuracy and so on. Thus it can not meet high measuring standards. A digital lock-in amplifier which is achieved with Digital Signal Processors (DSP) transfers analog signals to digital signals for processing. Though doing so could improve the device performance to a certain extent, it still has a shortcoming. For example, enough data width is required to ensure the measurement accuracy in the application of space technology when high-frequency weak signal being detected. While the width of data bus in a digital signal processor is fixed, the increased data width should not be larger than the width of data bus. So the improvement of measuring accuracy is limited.There is possibility that it would fail to meet the requirements in this situation.Fortunately, highly-integrated Programmable Logic Devices (PLD) has rich internal logic resouces, which provide a novel solution.In this thesis, it is proposed adopting the technology of IP reuse to build a weak signal detection system with the method of correlating demodulation as its core algorithm. Works in the thesis includes:1. Study on the basic mathematic theory of weak signal detection and the core algorithm of correlating demodulation.2. Derive the algorithm applied on detecting discrete digital signals, along with its improved solution, from the basis of analog correlating demodulation theory. System model is built and simulated as well with Matlab/Simulink.3. Design of IP core: transfer the algorithm model into IP modules.(1) The whole IP core is combined of three functional modules, digital LPF, amplitude/phase solution module and signed multiplier module. Here in amplitude/phase solution module, CORDIC algorithm is used.(2) Write the Verilog HDL codes of these three modules, and use ModelSim for pre-simulation.(3) Use Actel Libero IDE to synthesize the system and the netlist is given.(4) Download to Actel ProASIC3 M7A3P1000 FPGA to achieve.