Research On Low-power Digital FSK Demodulator

With the development of RF CMOS design technology, it is necessary to integrate RF transceiver in a single SOC chip. In recent years, short-distance low-power and low-cost wireless communication products have found more and more applications. The key and difficult point in wireless transceiver design is to decrease the power consumption. The FSK wireless transceiver allows designers to use the high-efficient non-linear power amplifier and avoid fabricating the complicated AD converter. All of the above advantages make the FSK receivers to be more efficient in power and area performances. In addition, the power could be optimized further if the demodulator is designed with digital circuits in a FSK receiver. So it is much critical to research on low-power digital FSK demodulator.The thesis focuses on the study and analysis of various architectures and circuits of FSK demodulators, and compares the performances with different demodulating methods and circuits. The frequency offset cancellation and low-power optimization technologies are emphasized specially as well. Then a new digital FSK demodulator based on a moving-window has been suggested. With this technology, the frequency offset cancellation can be realized automatically without any additional penalty. Due to the digital design features, this demodulator not only has a simple architecture, but also can be optimized with the help of the advanced EDA tool to reduce the power further.A digital FSK demodulator, which follows the rules of Medical Implant Communication Service, has been coded with Verilog HDL. The design method as well as its performances is also introduced. According to the simulation results with the noise being imposed on the IF signal, the demodulator achieves its demodulated BER 0.1% when the input SNR is 16.22dB, satisfying the specification. The simulation also shows the excellent frequency-offset cancellation capability of the new architecture.In the physical implementation, some optimization technologies are applied from the RTL level to gate level and layout phase to lower the power consumption effectively. The layout of core circuit occupies 0.027 mm~2 and consumes 100.000μW average power with 0.18μm CMOS technology and 1.8V power supply.