The Research Of General Modem Algorithms In(D) PSK And GFSK System For LPWAN

In the background of the Internet of everything,especially for the low power wide area network wireless communication system,applicable to general GFSK and PSK modulation demodulation system because of its modules share in limited hardware resources to achieve the versatility of the system,help to reduce the cost of communication system and power consumption,which have important research value.As ever-increasing requirement of low power wide area network for coverage,improve communication equipment demodulation Ber performance is increasingly important,but the hardware system of low cost,low power consumption requirement restricts the system complexity.This thesis is written for LPWAN based on general GFSK and(D)PSK modulation demodulation system,aims to improve the demodulation system Ber performance,reduce the algorithm complexity and hardware resource consumption.building the whole transmitter signal modulation and receiver signal demodulation from the launching packet process to the receiver of the overall physical simulation environment,and improve the transmitter modulation and receiver demodulation algorithm.On the basis of completing the algorithm design,hardware modules are designed for transmitter modulation and receiver demodulation.Finally utilize the FPGA platform to validation.The main innovation points of this thesis are as follows: 1.Proposed the general baseband modem architecture of GFSK and PSK system.On GFSK system transmitter increase PSK phase mapping branch,at the receiver change phase compensation threshold realized PSK system phase domain demodulation,get the general baseband modem architecture.In order to reduce the system hardware resource consumption and the complexity,.By enabling appointed module branch sharing the remaining modules in hardware.In order to further reduce the hardware resource consumption,by configuring different enabling signal control the rotation mode of Cordic,realized the prestored rotation Angle and all three of the critical paths shared respectively,and then realize the function of phase amplitude transformation and orthogonal phase function.2.Proposed the secondary estimate compensation algorithm of frequency offset,Improve the accuracy of phase offset estimation.meanwhile designed the oversampling interpolation zero method to get the local correlation sequence aims to reduce the hardware resource consumption of cross-correlation in packet detection module,and the method of add operation in realize the cross-correlation calculation reduce the hardware consumption relative to the traditional original data sampling interpolation method by more than half.Under the control of the packet detection module setting flag can also make primary secondary phase estimate compensation branch respectively,but achieved the aim of reducing the power consumption before the valid packet come and realized the phase offset value accurately estimate after the valid packet come,improve demodulation system Ber performance.3.Proposed the phase singularities compensation algorithm.In order to improve the demodulation packet error rate and bit error rate performance in low SNR condition,proposed the phase singularities compensation algorithm on the basic of the phase offset estimate consumption algorithm,after the valid data packet synchronization signal enabled,according to the comparator decision make the opposite sign compensation in these points which phase map excessive on the disturb of the low SNR noise,and the get more ideal phase demodulation signal.In hardware these can be easily realized by comparing complement addition.4.Proposed the Viterbi phase domain demodulation algorithm based on the Viterbi algorithm thought for GFSK system firstly.Relative to the threshold determination method,by using the cumulative measure value of maximum likelihood decision the survived path,the demodulation Ber performance is better,relative to the amplitude domain Viterbi demodulation algorithm,due to adopt the way of complement addition method relative to multiplication method to calculation path cumulative,reduces the computational complexity and the hardware resource consumption.In hardware implementation,by not choose the invalid cumulative calculation module of the chip selected signal corresponded which output full scale signals,result in the minimum value comparison subsequent can still get the right ways of surviving the index value,reduced the complexity of the control logic,meanwhile ensure the correct implementation of system function.