Design And Implementation Of Loop Filter For H.264 And AVS Codec

H.264/AVC and AVS are new generation of video encoding standards. Currently, it is a focus how to design a codec chip that supports both standards. This paper develops a hardware architecture of the multi-standard loop-filter that can be used for both standards in various codec systems. The verification and analysis are also presented.This paper gives a concise comparison of two kinds of loop-filtering algorithms, and also introduces the key techniques of digital integrated circuit design. The commonly used techniques for video systems and loop-filtering are discussed. The author presents a solution and the key points.From the perspective of hardware design, this paper analyzes the loop-filtering algorithms of H.264 and AVS and develops an algorithm that supports both standards. This algorithm has more flexible orders of filtering. Merging and simplifying both filtering algorithm by factoring, the algorithm reduces the numbers of adders to 1/2 of the standard filtering algorithm.Based on the algorithm above, this paper designs the loop-filter architecture for H.264 and AVS. The filter is divided into logic filtering module and process control module. The logic filtering module implements the loop-filtering algorithm. The process control module mainly controls the filtering process. The logic filtering module increases the maximum frequency by the pipeline design and reduces the chip area by the algorithm optimization. By optimizing the filtering process, the process control module keeps the pipeline fully busy, reduces the clock cycles of processing one macro block and lower the minimum frequency of real-time filtering. In the meantime, the module takes advantage of on-chip cache to reduce the pressure on the system buses.Finally, this paper implements the loop-filter by using HDL and performed the simulation and verification. The simulation result shows the architecture this paper develops is able to filter one macro block of 4:2:0 formats within 192 clock cycles. This reaches the minimum value of single filter design. The HDTV signal can be processed in real-time at 94MHz. After synthesizing, the analysis shows that, with 0.18 manufacturing techniques, this design can support the frequency of up to 220MHz and meet the requirement of real-time high definition decoding of 1080p signal.