VLSI Design And Research On Hardware Reuse Based H.264 Prediction Module

With highest data compression rate,The H.264 became the most popular video standard. However, it achieve high data compression ratio at the cost of high complex computation. This paper explore the hardware architecture of high-performance, low power, low cost h.264 prediction engine. Base on the time-multiplexing of hardware resources, the target architecture saves the power consumption and cost greatly by reducing the area of intra prediction module without affecting the coding performance. Main research topic and innovation points include:1,Hybrid multi-layer pipeline for h.264 decoding. Video decoding is macro block pipelined according to the task partition. The computation of intra prediction mode and the computation of inter motion vector are arranged in the fist pipeline stage together with bit-stream parsing and CAVLC decoding to balance the load between pipeline stages. In the second pipeline stage, prediction, IQIT and reconstruction before de-block are 1x4 parallelized to save the temporary synchronization resources needed for reconstruction. Under the macro block layer pipeline, there is a 4x4 layer two stage inter compensation pipeline. Which is adopted to rise the throughout of the inter compensation. The 4x4 sub macro block can be decoded in various orders according to the partition type and sub partition type of P macro block. By adjusting the 4x4 sub macro block decoding order, the reference pixel can be shared between 8x8 partition, which reduces the number of memory access, improves pipeline efficiency and saves power consumption.2,Reuse hardware resource between intra prediction and inter prediction. Base on the macro block layer pipeline, Reusable hardware resource is explored both in the same pipeline stage and across the pipeline stage. As a result, the area of intra prediction module is reduced significantly.