Implementation Of Variable Step-size Constant Modulus Blind Equalizer On FPGA

Channel equalization technology is the key technology of modern digital communication system. It can eliminate the problem of inter-symbol interference effectively and improve communication quality. Blind equalization became a hot topic because it does not require training sequences in channel equalization techniques. With the in-depth study of blind equalization algorithm, how to applied blind equalization algorithm into realize become new issues.The rapid development of technology in integrated circuits and the programmable logic device support blind equalization applications. This dissertation consists of designing and implementing a blind equalizer system that is compatible with constant modulus blind equalization algorithm on FPGA. The main works of this paper can be summarized as follows: ( 1 ) after optimized variable step-size constant modulus blind equalization algorithm, it can avoid the division in the form of computation and improve the efficiency of the hardware.(2) This paper design variable step-size constant modulus blind equalizer based on floating-point operations. This equalizer consists of serial sub-blocks. So every sub-block is independent in function with others. It can be altered to adapt different algorithm by means of change the corresponding sub-block. This way facilitates studies henceforth.( 3 ) This paper design test platform which includes a signal generator, display controller and counter of error, at the same time variable step-size constant modulus blind equalization algorithm is verified. Platform outputs experimental results of emulated system as data and graph. The results show that the error rate, convergence speed and channel tracking capability preferment well in the design of the blind equalizer.