The Optimal Design Of Fixed-Point FIR Digital Filter Implemented Using FPGA

As a basic function unit of digital signal processing, finite impulse response (FIR) digital filter has been widely used in many applications such as communication, radar, image and speech processing. The design and field-programmable gate array (FPGA) implementation of FIR digital filter with linear phase are discussed in this dissertation, whose main contents are as follows:1. The design of linear phase FIR digital filters based on the constrained optimality criteria is performed within the real-valued domain using second order cone programming, with the condition of coefficient symmetry satisfied strictly. The unified mathematical expression is developed for the design problems, and the generalized solution frame is built upon the second order cones corresponding to the constraints of maximum error and squared error.2. The method of iterative quantization is developed for designing linear phase FIR filters with discrete coefficients based on the peak constrained least squares criterion. The traditional multiple exchange algorithm is modified to obtain some continuous coefficients when the others are fixed, and the resulted algorithm is combined with an iterative procedure in which all the coefficients are quantized one by one.3. A new discrete Lagrangian local search method is presented for the design of FIR filters with low coefficient complexity based on the peak constrained least squares criterion. In the proposed local search,the geometric property of the objective function, which characters a hyper-ellipse, is utilized to verdict the invalid points in the discrete space and lead to the improvement of search efficiency.4. A novel architecture for implementing distributed arithmetic (DA) is proposed to speed up the FPGA-based FIR filter with the direct form. By employing the carry save technique, the new serial and parallel distributed arithmetic architectures are presented, in which the carry chains are segmented and the temporary results are divided into partial sum and carry bits that are summed outside the critical path. As a result, the original delay of critical path is reduced.It is of certain significance in both theory and engineering for this work to exploit some new approaches for the design and implementation of FIR digital filter with linear phase.