| X processor is a microprocessor developed by National University of Defense Technology. It adopts intel's x86 instruction set, ultra scalar technology, two levels of enhanced branch prediction technology, and internal cache of Harved structure. However, the complexity of pipeline control increases due to these technologies. How to control the instruction pipeline effectively, becomes the research focus herein.This paper presents the instruction's stamp mechanism of X processor. This mechanism is used to solve this problem. In detail, we have set up stamp for the instruction prefetched from cache or memory, to control the instruction in the pipeline dynamically. In the concrete design, we adopt prefetch buffer to improve speed of fetching stamp streams. We also adopt barrel shifter with pre-charge structure for the same purpose. We also use specially designed FIFO to solve the blockade problem that may exist in the pipeline. We also put forward the testbility analysis of our design, a kind of built-in-self-test of the stamp mechanism, a structure of scanning chain.To verify our stamp mechanism, we have built module and chip level simulation environment respectively. Simulation of the key module of the stamp mechanism has been carried out under different working modes. The verification results indicate that this mechanism satisfied the design requests. The correctness of our design has already been verified by actual X processor chip. |
