Research And Implementation Of Key Modules For H.264 Video Decoder

As compared with existing standards, H.264 has many new features that make it the most advanced performance. Now H.264 has been widely used in digital video communication and storage. Increasing VLSI processing capacity is the foundation of implementation of H.264 algorithm.This thesis researchs key modules of H.264 video decoder, including VLD, Reorder, Inverse Transform, Inverse Quantization, Intra prediction, Motion compensation, Deblocking filter, et al. On this basis, we design the H.264 decoder chip for 1280×720 resolution HDTV format video for 30 f/s real-time decoding. The research results are as follows:1,Intra prediction in the H.264 video coding standard can enhance compression rate whereas its multi prediction modes bring difficulty for VLSI implementation. A high parallel intra predictor generator using numerical strength reduction algorithm was designed, which gets rid of redundant operations between seventeen prediction modes and can get sixteen samples'prediction value every clock cycle. As compared with existing approach using reconfigurable architecture, our design has less area and simple control logic.2,The deblocking filter in the H.264 video coding standard can improve video quality but with huge computational complexity. A high performance, small area deblocking filter was designed based on a deblocking algorithm, which executes read/write operations on external memory with filtering computations in parallel based on an advanced filtering order. Our design has less area and better performance than other deblocking filters.3,The H.264 video decoder chip was implemented in 0.18μm process by Verilog. The results show that it can achieve 33 f/s for 1280×720 resolution HDTV format video at 120 MHz with an area of no more than 130k gates.