Research And Hardware Implemention On Stream Memory Controlling System Technology

Stream architecture aims at media and signal processing , graphics, and scientific computing. It's been paying more and more attention in the field of new rising computer architectures. The presence of data parallelism in an application provides two important opportunities to achieve high performance - the parallelism itself, and latency tolerance. The memory hierarchy of stream architecture privides a suitable platform to hold those two opportunities.The memory hierarchy of stream architecture comprises Local Register Fils(LRF), Stream Register Filses(SRF) and Stream Memory Controlling System(SMCS). This thesis focuses on techniques of the SMCS which is loacated outermost of the memory hierarchy. A particular introduction about internal registers, address generators, and interface buffers, which comprise SMCS, is presented. The emphasis is put on the three memory access modes, and the process how they works. A method of design and hardware implementation based on a high performance stream processor is presented, as well as the comparing synthesis results of some different designing way.An improved method of the SMCS aims at reordering the memory access sequence is presented. The simulation result shows that the method can make an efficient way of the memory accessing. In order to provide better bandwidth support for the upper layer, a new SMCS architecture based on multi-bank interleaved is presented.