Research On Logic Debugging Techniques In Equipment Checking

How to make the design of integrated circuit correct and valid is the biggest challenge, as the scale and complexity of VLSI circuit design increase, logic design errors become inevitable. Once a verification tool finds some errors in the integrated circuit designs, error location and correction must be done by designers. So, it is necessary to research and develop an approach for error diagnosis and correction with good expansibility that the working efficiency is high, and searching time is short. The simulation-based approach is an appropriate solution currently.In this thesis, the simulation-based approaches and the symbolic approach for logic debugging are studied systematically. Meanwhile, we put forward improvements to some heuristic algorithms based on the primary approaches and get some conclusions and achievements. The main work is as follow:1. Several main approaches for error diagnosis and correction are studied, analyzed and compared. Theoretical research and analysis proof of diagnosis approach are given, based on which, probabilistic idea is used to the observable measurement.2. We apply symbolic simulation technique to the region model and optimize the error diagnosis approach of based region-model. Feasibility analysis and steps of optimization process are given.3. We apply the slicing technique to debugging of corresponded hardware description language. And take experiment to the hardware description language, the results show that the technique can reduce the region which contains errors greatly.4. We design the whole flowchart, structure and the core algorithm of a debugging module which uses the simulation-based approach, give the file description and data structure used and introduce the related research topics.