Design And Implementation Of Key Algorithms For OFDMA Receiver Based On IEEE802.16e Standard

This paper focuses on key technologies of the downlink OFDMA receiver for IEEE802.16e standard. On researching the algorithms and implementations of Signal Synchronization, Channel Estimation, Channel Equilibrium and LDPC error correction code under fast moving channel, we simulate performance of key schemes and show the hardware design based on FPGA.In this paper, we show a frame synchronization process based on coarse decation and fine detection. This structure not only decreases possibility of error dectection but also system power consuming. In order to share modules in time domain synchronization block, frame synchronization block and time domain frequency tracement & adjustment block are combined together.For the unbalanced structure of downlink pilot of PUSC mode, we supply a two-dimension linear interpolation for channel estimation, and then show the structure for hardware implementation based on FPGA. Because 16e support fast moving channel, a real-time channel tracing algorithm is used to recover signals. In the process of signal equilibrium, cordic and HUNG alogorithms are employed that turns complex devision to real multiplication and phase rotation.In chapter four, basic conception of LDPC code is introduced first. Two direct encodingschemes——RU and block encoding algorithms are researched and operation complexity aregiven in this chapter for each algorithm. A hardware software co-encoding scheme is used to make the encoder to fit different code length and code rate. Pipeline structure for block encoding is shown and hardware complexity is also given.A shuffled iterative decoding concept is introduced and researched in this paper to accelerate the convergence speed of BPA. Two forms of shuffled iterative decoding algorithm is given. A layered decoder structure is shown to support semi-parallel decode. It is proved that the layered shuffled iterative decoding algorithm is in accordance with BPA. Two serial structures of the layered architecture are introduced to make the scheme fit different hardware designs.Block-serial and semi-parallel architectures of LDPC decoder are shown in the final chapter of this paper. As layered shuffled decoding algorithm is used, throughtput and memory efficiency of this decoder are improved. Comparing with classical serial architecture, block-serial decoder in this paper is much more flexbile and can support different code lengths and code rates. Approximate-Min Scheme is used to increase memory efficiency during serial message processing. Semi-parallel decoder in this paper not only has a high throughput, but also has a hardware complexity configurable structure.