Hardware Implementation And Improvement Of LS Channel Estimation In GMC Mobile Communication System

All around the world, the research for technology of the next generation of wireless communication has been carried out. National 863 FUTURE Project has set the goal of the new generation cellular mobile communication system. According to this, NCRL (National Communication Research Laboratory) of Southeast University has introduced a new transmission technique called GMC-TDD-xDMA (Generalized Multi-Carrier Time Division Duplex x-Division Multiple Access) to implement the plan of high efficient packet data transmission with peak data rate not less than 20Mbps. Channel estimation is one of the important part in this project. Having taken this as a kernel and based on the system plan, LS(least square) method has been investigated, its hardware implementation has also been considered. Through the research of the algorithm and problems occur during hardware design, the PAST algorithm is introduced to improve the efficiency and so form a new plan for channel estimation.In the design, dual cyclic prefix is adopted which make the guard interval of adjacent time slots composed of the cyclic prefixed pilot sequences. By doing this, the inter-block interference, as well as the influence of data segments on pilot sequences will be eliminated; at the same time, the received signal can be constructed as no longer the linear convolution, but the cyclic convolution of the transmitted signal and the channel impulse response. Thus, the received signal vector can be expressed as a product of the transmitted signal vector and a cyclic matrix that is composed of channel impulse response vector. With all these advantages, a receiver of low complexity and high performance can be designed.After some simple introduction of traditional and novel methods for channel estimation, based on different time slots structure and the investigation of the performance of LS, one kind of time slot structure is selected for hardware design. With FPGA the hardware design of channel estimation is implemented. A feature called pipeline architecture is introduced to reduce the complexity and improve the efficiency of hardware resources. After the hardware implementation, software test ensues to verify the feasibility of hardware module. The latter is also downloaded in the whole system for co-debugging.When the work of hardware implementation is done, according to the problems arise during the design and the characteristic of LS method itself, the design of time slots structure is improved. Three new time slots structure corresponding to low, medium and high speed is assumed. Based on feature of such structure, PAST algorithm is introduced. Combined with the former LS method, a new scheme for channel estimation is proposed. The suggestion for enhancing the performance is proposed after looking into the results of simulation and comparison with former method. At last, according to the results, a new hardware structure is presented.