A Heterogeneous Multiprocessor Simulator Based On SimpleScalar With Extensions For Memory And Bus

With the development of system-on-chip (SoC) and embedded systems, heterogeneous multi-core processors begin to come into people's life. In order to shorten the development cycle and save costs, a system-level multi-core simulator is in need. However, due to the lack of system-level simulation platforms for multi-core heterogeneous processors, the research on multi-core heterogeneous processor simulators just starts to evolve distinctly.This paper proposes a simulation methodology with implementation of a heterogeneous multi-core simulator. The heterogeneous multi-core simulator is based on SimpleScalar integrated with a SystemC framework, which deals with communication, and synchronization among different processing modules. Inter-core communication is enabled with a shared memory scheme incorporating a set of shared memory access instructions and communication mechanisms. In addition, a synchronization mechanism, which switches execution of processor components only when communication occurs, is proposed for efficient cooperation among multiple cores on single application. Furthermore, through the bus interface extended from shared memory, other modules can be easily integrated into the simulator framework, to achieve a more complicated co-simulation.Experimental results show that our simulator correctly simulates the behavior of a multi-core processor as well as inter-core communications. The simulator also demonstrates a convincing performance on Linux PC platforms.