Font Size: a A A

Design And Research On CMOS Direct Down Conversion Mixer For UWB System

Posted on:2008-11-12Degree:MasterType:Thesis
Country:ChinaCandidate:Q K LiuFull Text:PDF
GTID:2178360212474926Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the rapid development of wireless communication in recent years, Radio Frequency Integrated Circuit (RFIC), which is a crucial block of it, has become a focus of present study. The development of CMOS technology greatly improves the performance of the devices and makes it possible to substitute CMOS technology for the traditional GaAs and BiCMOS technology in RFICs. However, some second-order effects and substrate crosstalk etc. will also become more obvious, which brings much difficulty to the circuit design, and the most severe consequence is a reduction of the voltage supply, which causes that not all circuit topologies can satisfy the required specifications.The mixer is an important block in RFICs, as every wireless communication system needs at least one mixer, and its performance has a direct influence upon that of the whole system and upon the demands of the system for other blocks.To solve these problems, this paper presents a high performance, namely low voltage, high linearity and high conversion gain, CMOS direct down conversion mixer for UWB (Ultra Wide Band) system. Based on the traditional Gilbert mixer, the proposed mixer makes many improvements upon it, including the uses of folded topology, inverter, self-biasing, constant Gm biasing circuit and so on. Also, inductor in LC resonating network is used to get rid of the negative effect of parasitic capacitor. Consequently, all performances of the mixer are effectively enhanced. This paper gives a detailed analysis of the proposed mixer, and at last, this paper gives some suggestions on how to improve the performance of the mixer.This design is based on 0.18μm CMOS RF technology of SMIC, employing Spectre RF to accomplish the simulation and using Virtuoso Layout Editor to finish the layout design, and finally, the layout taped out in SMIC (Shanghai). the simulation results show that the conversion gain of 10dB, the P1dB of 9.5dBm, the IIP3 of 15.1dBm, the DSB(double side-band) Noise Figure at turning point of 11dB and at 100MHz of 9dB. The circuit operates at the voltage supply of 1.8V and dissipates 11mW.
Keywords/Search Tags:UWB, folded topology, inverter, self-biasing, constant Gm
PDF Full Text Request
Related items