Performance Of Quantized TTCM And The Design Of Its Decoder Based On FPGA

As a new bandwidth-efficient coded modulation scheme, Turbo Trellis-Coded Modulation (TTCM) has recently received much attention in channel coding of digital communication systems due to its near capacity performance and high bandwidth-efficiency. It has an overall structure similar to binary Turbo codes, but employs Trellis-Coded Modulation (TCM) codes (including multidimensional codes) as component codes leading to a straightforward encoder structure, and allows iterative decoding in analogy to the binary Turbo decoder. However, certain special conditions may need to be met at the encoder, and the iterative decoder needs to be adapted to the decoding of the component TCM codes. A soft-in and soft-out component decoder can be implemented using the maximum a posteriori (MAP) or the maximum likelihood (ML) decoding algorithm. While the MAP algorithm offers better performance than the ML decoding algorithm, the computation is complex and not suitable foe hardware implementation. The LOG-MAP algorithm we derived, which performs necessary computations in the logarithm domain, greatly reduces hardware complexity. Simulation results are presented and compare the scheme with traditional TCM. The results show that the novel scheme is very powerful, yet of modest complexity since simple component codes are used.With the proliferation of the battery powered devices, power dissipation, along with speed and area, is a major concern in VLSI design. In this thesis, we investigated a low-power design of a Turbo TCM decoder based on the sliding windows LOG-MAP algorithm. Our Turbo TCM decoder has two component LOG-MAP decoders, which perform the decoding process alternatively.The main results and contents are as follows.1. Computed LOG-MAP algorithm of TTCM, and analyze performance of quantized TTCM, with different times of iterative in decoding.2. Designed decoder of 2-dimension 8PSK TTCM with FPGA.3. Improved the encoder and decoder of TTCM, to make it be fit for systems with high processing speed.The decoder was described in VHDL under the Quartus.