The Design And FPGA Implementation Of RS Code Card Based On PCI Bus

In this thesis, the theory of error-correcting codes, the encoding and decoding algorithm of RS codes, the standards of PCI bus and the technologies of FPGA are studied deeply by designing the RS code card that is applied to AOS systemError-correct code has played more and more a role in the communication system. As a kind of the linear block codes, RS code is widely used in digital communications with the powerful error-correcting capability. In this thesis, on the basis of the encoding-decoding algorithms, implementing paths and relative technologies developed in these fields, RS code card is implemented with FPGA.Due to its excellent performance such as bandwidth of the data, power dissipation, noise immunity and opening property, PCI bus wins rapidly increasing popularization and extensive application in the embedded system and the industrial control system. Have studied and analysed PCI bus standard deeply, the PCI bus controller is implemented with mealy state machine and FPGA.Several aspects are included in the thesis:1. Analysing deeply the theory of error-correcting codes and studying deeply the encoding and decoding algorithm of RS codes.2. Several basis cells, such as add, multiplication and inverse in the encoding and decoding algorithm of RS code, are researched. On this basis, the multiplication module is optimized.3. The RS encoding algorithm is implemented by using the basis cell which is mentioned above.4. The architecture design of RS decoding algorithm is emphasis. The algorithm includes several parts: Syndrome Calculator, Key Equation Solver, Chien Search and Error Value Evaluator. The design is implemented by using the inversionless Berlekamp-Massey algorithm. This architecture achieves an optimization in the area-delay product.5. Research and analyse deeply the PCI bus standard.6. The top-down design methodology is used to realize the PCI bus controller. This controller has six modules, such as PCI Top, Configuration Multiplexer, Base Address Check, State Machine, Parity Check and Glue.