IP Modeling For On-Chip Cache And MMU

System-on-Chip (SoC) generate due to the rapid advances in integration technologies and processingtechnologies. However the performance gap between microprocessor and off-chip memory becomes thebottleneck of the high performance of SoC. Now on-chip Caches are widely used in order to solve thisproblem, and many new structures are proposed to improve performance or to low the power dissipation.National Engineering Research Center for Application Specific Integrated Circuit System of SoutheastUniversitydesigntheCache,MMUandwritebuffercircuitsusingcustomapproach.The custom block should be reusable, and it will be better if it can be provided to other designer ashardIPcore.AsIntactIPshould includefunctionalmodel,timingmodel,physicalmodelandtestmodel,inthis paper, we focus on building the functional and timing model for Cache/MMU. First we analyze thedifferent methods for modeling timing, and then made the timing model use the timing informationcollected fromdynamicSPICE simulation. On theotherhand, associate with the customcircuits, we madethe behavioral description Verilog model for the macro block on the base of deeply understanding of thestructure of Cache/MMU. Using functional model instead of SPICE net-list can speed up the simulationhighly, and the correct functional model also provides the possibility to seek after a new cache structurewhichcanimprovetheperformanceofCPUbetter.In terms of the timing model, Cache/MMU was synthesized in the SoC chip Garfield. Garfield hastaped out in SMIC with 0.18?m process. We tested the chip with the help of ARM Development Suite(ADS). The test results indicate that CPU can do correct calculation, and Cache/MMU also can workproperly. As to the programof calculate?, the work frequency of CPU is up to 98MHz when the programis loaded in SDRAM and when the program is loaded in eSRAM, the work frequency is up to 150MHzwithCachedisableand104MHzwithCacheenable.The functional model has passed the simulation using VCS in the system of Garfield. It can executethe memory protect, Cache replacement, disable Cache and disable TLB correctly, and also calculate ?correctly. The simulation time reduced from 10days to 5 minute for the programof 2.4k, includeing 1888instructoions.