Design Of The Viterbi Decoder And The Rake Receiver

Convolutional Coding is an error-control coding to process continuous data stream. The Viterbi decoding algorithm is a type of maximum likelihood algorithm for memoryless channel. The Convolutional Coding employed with Viterbi decoding algorithm has already become indispensable channel coding scheme in modern communication systems.RAKE receiving is a very effective method against multi-path fading in CDMA system. It separately demodulates each received signal, and then overlaps output to enhance the effect of receiving.The Viterbi decoder with hard decision designed by the paper, is aimed at (3,1,9) Convolutional coding. The data rate is 9.6kbps. The data rate received by the RAKE receiver is spreaded by 127-bit spread sequences, added pilot signals and modulated by QPSK. Both Viterbi decoder and RAKE receiver under ISE environment of Xilinx corp. are implemented with the Verilog HDL.First, the paper briefly introduces theories of Convolutional Coding, Viterbi decoding algorithm and RAKE receiver. Then, the paper focuses on methods to implement Viterbi decoder and RAKE receiver in FPGA. The two methods, an all-parallel Viterbi decoder and an optimized Viterbi decoder are represented. The former one is small constrained, simple construction and large resource consuming while the latter one is long constrained, complicated construction and small resource consuming. Employing the digital circuit optimize algorithm, the latter one has already covered design thoughts of present Viterbi decoder. For the design of RAKE receiver, a receiving with delay and unfixed channel estimation coefficients, integrating channel estimation, capture of spread sequences and, despread, are described. Its features are real-time, quick capture and easy implement. The design is verified with synthesizing and simulation.This paper describes the methods to design Viterbi Decoder and RAKE receiver, owns some theoretical and practical significance.