Research Of The Rake Receiver On FPGA

Code-Division Multiple Access(CDMA) became the primary technology of thethird generation mobile communication system due to its unique capability ofanti-interference, multiple-access and multipath-division. Rake receiver is one of thekey technologies in CDMA system. With the fast development of communicationtechnology, the Rake receiver with its effective anti-interference ability is always hotpoint to be studied. people constantly improve the conventional Rake receiver toacquire better performance. With the rapid development of FPGA, the traditionalmethod of the design of digital system was changed largely. FPGA has the advantagesof large scale, small investment in the design course, short period of design and goodsecrecy. The application of FPGA brought us much convenience for the research ofRake receiver.This thesis aims at designing a kind of Rake receiver with low power and simplehardware structure. At first, interrelated elements of Rake receiver was introduced, itsanti-interference ability was analyzed. Then, we compare some kinds of Rake receiver.A kind of improved flexible Rake receiver was presented. This Rake receiver adoptdifferent buffer structure,it can economize a lot of hardware resource, and the Rakereceiver has low power. At last, we designed primary modules with Verilog HDL andemulated with software ISE 6.2 of Xilinx Inc. The emulator platform is XC3S1000chip of Spartan-3. the results of emulator prove this design to be right. The designedmodules can be replanted in similar system easily. As a result, the achievements of thedesign are of practical values.