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Design And Implementation Of Hardware Network Information Filter System Based On FPGA

Posted on:2007-05-20Degree:MasterType:Thesis
Country:ChinaCandidate:X B YangFull Text:PDF
GTID:2178360185985663Subject:Computer Science and Technology
Abstract/Summary:PDF Full Text Request
With the wide spread of internet, network information security have more and more come to the spotlight. While firewall has done a great job on access control, it has done little about the data package content; and the software content filter technique can secure the safety of information, but with intolerable speed. Hardware Network Information Filtering system is a way out by combining the functions of fire wall and content filtering. Thus the research on and the design of efficient Hardware Network Information Filter system is highly in demand.Firstly, this paper does a thorough research on different firewall techn-ologies and content filter algorithms, proposes the idea of two-stage network information filter. The filter process is divided into the stage of access control and that of content filter, of which the former one deals with the information of fixed deviation in the data package and the latter one deals with the specific content of data packages. To get a high throughput, the good design of these two parts is very important.Secondly, design different scheme s to the two parts.State Inspection fire-wall design technique is used in access control. The network fluxes are classified as secure, suspicious, or repulsive using the Rules Collection, and only the suspi-cious ones will be handled to next stage.Furthermore, Using the idea of cache, the paper proposed the States Collection structure. States Collection and Rules Collection together enable efficient access control. Among options of different content filtering methods, the State Machine-based plan is selected, which is more appropriate for hardware design. And based on this, the concept of unit filter module-Servo is presented, and the implementation of the Servos' Array enables parallel filtering and enhanced the performance of content filter module.In the end, all the proposed functions are realized based upon FPGA technique and the rationality and validity of the design is tested through simulation.
Keywords/Search Tags:Hardware Information Filtering, Access Control, Rules Collection, States Collection, Servos' Array
PDF Full Text Request
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