Implementation Of H.264 Encoder Based On TMS320C6416

In the information society, the information, especially the video information is on the increase with a velocity of exponential magnitude. And it is too large to store or transmit. So the vedio compression coding is becoming a focus in the communication research. In March 2003, JVT (Joint Video Team) of ITU-T VCEG (Video Coding Experts Group) & ISO/IEC MPEG (Motion Picture Experts Group) published a video compression coding international standard, which will be two identical standards: Part 10 of ISO/IEC MPEG4 and ITU-T H.264.H.264 offers significantly better video compression efficiency than the previous ITU-T standards and MPEG standards, but its computational complexity is too large for implementation. So the computational complexity has become the bottleneck for the implementation of H.264 encoder in engineering. Especially it is hard for the implementation in real-time.Based on the analysis of H.264, the encoder is implemented on TMS320C6416 with paralleling arithmetic and optimization methods. More specifically, this dissertation includes following contents:Firstly, based on the analysis of H.264, the effect on coding efficiency by the key modules of H.264 is analyzed. Secondly, for the purpose of improving the efficiency of H.264 encoder, we optimized the H.264 arithmetic. Especially fast motion estimation is improved by using HUCMHGS (Hybrid Unsymmetrical-cross Multi-Hexagon-grid Search) for integer pel motion estimation and using CBFPS (Center Biased Fractional Pel Search) for fractional pel motion estimation. Thirdly, the paralleling arithmetic and optimization methods of H.264 are studied. Based on the configuration features of TMS320C6416, the encoder of H.264 is implemented by using assembly language.The H.264 encoder that we have implemented on TMS320C6416 has a high processing speed. It can comprocess 27.5 frames of QCIF video images per second in real-time when the CPU frequency of TMS320C6416 is 720MHz.