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24 Fixed-point DSP Parallel Multiplier Design

Posted on:2007-10-28Degree:MasterType:Thesis
Country:ChinaCandidate:H X ChenFull Text:PDF
GTID:2178360182999950Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
The parallel multiplication accumulator is an important section of 24 fixed-point DSP which is developed by the Beijing MXH microelectronic technology limited company. The circuit uses the reversion design method with Wuxi Chinese 0.6 μm CMOS craft technology. The present paper primary mission is reorganize circuit and circuit simulation after the parallel multiplier original domain electric circuit, The parallel multiplication accumulator (MAC) has three main parts: The partial product producer (Booth Encode unit), the addition array unit (Mult unit) and carries transmits adder(ACC unit). Producing the partial product is the main function of the partial product producer;The addition array block completes to the partial product selling and buying of real esgate within the same family;Carries transmits the accumulator is adds together all partial products and produces the 2n position result for produce the final outcome.The partial product producer mainly uses the Booth II algorithm, reduced the partial product number greatly which in the multiplication accumulation operation produces, thus enhances the entire multiplication accumulator the operating speed;The addition array module uses the CSA array accumulator, the transmission delay which with Wallace the Tree structure, reduced the massive partial products adds together when produces, optimized the partial product accumulation process, enhanced the whole operating speed;Carries transmits the accumulator to use for to complete the entire MAC unit the most earlier stage accumulation operation, uses the partition to carry the way, enhances the most earlier stage the operating speed.After the electric circuit reorganization and the analysis, the paper uses the Hsim simulator for the entire electric circuit to carry on the simulation. Compiles the Hsim test document according to the MAC unit 20 program. The simulation test proof, under the 40MIPS working mode active status, the entire multiplication accumulator stage functionis correct.
Keywords/Search Tags:parallel multiplication, circuit design, circuit simulation
PDF Full Text Request
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