The Study And Design Of Real Time Image Collection And Denoising System Based On FPGA

Image is one of the most important information among all information that weacquire,and image collection is widely used in the region of digital imageprocessing,image identification.Real time image collection and processing possessan important status in modern multimedia technology.In our daily lives,one of thecore technology of products like digital camera,video telephone,telephonemeeting is real time image collection,and collection speed and quality affectdirectly product's holistic effect.But,image signal is always disturbed by all kindsof noise when being produced,transmitted and being recorded,and this will affectoptical effect badly,so we must take some steps to decrease noise before we makemargin detection ,image partition,pattern recognition further.There are two main parts in the design,the first is real time image collectionused CMOS image sensor OV9121,the second is an designation of an specificintegrated circuits for mixed image filter to satisfy real time processing.The article consists of six chapters,the first chapter mainly introduce the wideuse of real time image collection,and the necessity of real time image processingwith ASIC.The chapter also comprise of the introduction of FPGA and its designflow,hardware description language Verilog HDL and its design software QuartusII.The second chapter mainly introduce the methods of image denoising,such asstandard median filter,standard mean filter,multi-level median filter,weightedmean filter,modified trimmed mean filter(MTM),MAD and mixed filter methodwhich consists of median filter and mean filter.we also compute the respectivefilter result and compare the filtering effect,we adopt the mixed filter method inthe design.The third chapter is the holistic scheme of the project.The chips adopted inthe project consists of one FPGA,one CMOS image sensor produced by OmniVision corporation OV9121 and two SRAM chips.OV9121 takes charge of imagecollection controlled by FPGA,and the two SRAM are image buffer storage,imagecollection and filter module is realized in the FPGA.The holistic scheme is figureone.VSYNCXCLKHREFPCLKSCCBmuxSRAMwriteenableVSYNCPCLKDATADATAPCLKOV9121SRAM1SRAM2SRAM control moduleFilter ModuleCLKPLLCLK1CLK2FPGADATADATAcrystalliodDisplay DeviceDATADATACLCKLKPCLKHREFov VSYNCinitializationmodulecollectioncontrol moduleFigure 1 Holistic scheme of the designThe fourth chapter introduce image collection part.This part consists ofOV9121 initialization module,image collection control module,SRAM controlmodule. Initialization module configure OV9121's work mode, resolution,frame frequency;Image collection control module provide control signal thatOV9121 need when collecting image,SRAM control module answer for imagedata buffer and deliver these data to filter module.This part can realize collect 25frame image in one second,and one frame image has 640×480 pixels,one pixelhas 256 gray .Change the parameter of initialization module,the design cancollect video image whose resolution from 2×2 to 640×480.The fifth chapter introduce the design of filter module.The filter arithmeticwe adopt is mixed filter,the holistic design scheme of filter module is figuretwo.The design consists of filter window formation module,noise style judgementmodule,multilevel median filter module,weighed mean filter module,and whenwe take boundary pixel into account,we need a counter module.The register isused to delay image data,so that the output of noise style judgement module andthe input of filter module are synchronous in clock time.In this part,we realizeread one data into filter module,and form one filter window and deal with onefilter window only in one clock time,and so the design satisfies real timedenoising.FilterwindowformationmoduleNoise style judgemoduleMultilevel medianfilterWeighed mean filterDataData enableRegisterMuxDataDataoutputcounterEnable or resetCounter numberFigure 2 Design of denoising moduleThe main work of the article are:1. Realize real time image collection using FPGA+OV9121.And changing theparameter of initialization module,we can change the image resolution that thesystem can collect from 2×2 to 640×480.2. Use pipeline technology,mixed image filter is implemented in one FPGA,andthe result satisfies real time processing.3. Use discaring data when comparing data,realize 3×3 window standard medianfilter in six level compare circuits.4. Design a special FIFO for filter window module.5. Use module The filter window formation module,standard median filtermodule,multilevel median filter module and weighed mean filter module canbe adopted independently as a part of many other image processing projiects.