The Design And Implementation Of Hardware System On HF Digital Processing

The paper is based on the two projects:" the third generation HF correspondence system" and "the research and implement on data transmission of the Very Low Signal-to-Noise HF correspondence ". In this paper we have discussed and designed the universal hardware system for the two projects,and completed and debugged it.We use two pieces of DSP processors and a piece of FPGA to be a coordinated work system , and have adopted the new chip to raise work clock of the system.And the system can process signal in real-time.The hardware system debugged can stabilize dependablely work. The combine debugging result of software and hardware of "the third generation HF correspondence system" and "the research and implement on data transmission of the Very Low Signal-to-Noise HF correspondence" indicates that the system designed come to the reserved design target,satisfying the request that signal for real-time handle. It expresses that we really have realized the digital processing of HF correspondence, carried out the data transmission of the HF broadcasting station and come to the design purpose.Finally, we made a certain research to the PN code synchronous algorithm within "the research and implement on data transmission of the Very Low Signal-to-Noise HF correspondence", and the Veterbi decode algorithm,channel adaptive equalization algorithm within "the third generation HF correspondence system".And the the PN code synchronous calculate way of " the research and implement on data transmission of the Very Low Signal-to-Noise HF correspondence " is realized in the FPGA, resulting the synchronous time shortenned.