Research On Design And Optimization Of Video Decoder

The development of the video coding and decoding technology makes the video compression ratio highly increased and the implementation more and more complicated.On the other hand, along with the development of VLSI design technology, more and more transistors can be integrated into one chip, and the design scale and complexity of the chip greatly increased. To design a chip with high quality and high ratio of performance to price, the optimization of the design is inevitable.This thesis tries to do some research on optimization design on the system, module and circuit level.The design and optimization on the system level mainly includes inter-connection of modules, data storing structure and SDRAM bus architecture. Based on the analysis of the performance of various data path and control path hybrid control scheme is adopted. After analyzing the data processing speed, data processing unit and data existing period, a local buffer architecture is proposed, which reduces the buffer size and eases the control. Pingpang architecture is adopted to optimize the memory structure. The Token Ring is used to reduce the hardware cost.On the module level optimization, the reconfiguration optimization is used in the design of intra-prediction module of AVS video decoder. Moreover, the reusable technology based on the operation unit is analyzed. One example is the reuse of the PLA unit in the Bitstream Parsing Unit.On the circuit level optimization, two logic circuit optimization methods, RaR and SRAR, are proposed. The optimization step of retiming and resynthesis can solve the problem of logic circuit redundancy efficiently and reduce the hardware cost. Moreover, a design method of high efficient finite state machine and a synthesis-oriented coding rule are proposed.