Research On Optimization For Prediction Algorithms In H.264 Encoder

With the development of the communication and computer, video compression technologies have become an significant part of communicate and consume visual information. It has been an active research area that how to convey source data with the highest fidelity possible using the lowest bit rate. Over the last one and a half decades, a series of international standards of video compression coding have been developed by International Standardization Organization (ISO) and International Telecommunication Union (ITU), which have greatly promoted the application of the video coding technology. The newest international video coding standard recommendation H.264 of ITU-T also known as International Standard 14496-10 or MPEG-4 part 10 Advanced Video Coding (AVC) of ISO/IEC is the latest standard in a sequence of the video coding standards H.261, MPEG-1, MPEG-2, H.263, MPEG-4.With these new tools, video compression in H.264/AVC codec is several times the most computationally intensive than other existing standards. The real-time video codec based on embedded processor have to reduce the complexity and demand more efficient algorithms. So the main endeavor of this work is to achieve maximal video quality and real time video processing speed through studying on the motion estimation, interpolation, deblocking filter and SAD/SATD.In this thesis, first, an introduced of the video coding theory and international standards is given. This work is focused on analyzing the new technical developments adopted in H.264/AVC coding features adopted by H.264 and spatial and temporal complexity.Second, as the most expensive module in H.264/AVC coding, motion estimation is analyzed. An improved algorithm of mode decision in motion estimation is proposed with the correlation of macroblocks. It makes use of the spatial homogeneity and the temporal stationarity characteristics of video objects. Thus only a small number of intermodes are selected in the inter prediction.Third, from the point of view of hardware application, an analysis of H.264 encoder is presented. An improved algorithm of mb-level (macroblock-level) interpolation and deblocking filter is proposed for H.264/AVC encoder adapted to the memory structure of hardware. In order to implement the encoder on an embedded processor, an efficient memory management scheme is also presented. Experimental results show our approach can greatly reduce the size of memory (93.1%) and cycles (31.8%).Last, an optimization of SDA/SATD is proceeding with the instruction characteristics of ADSP BF533 (BF533) and MD32 respectively.