Design Of Rf Front-End For Global Navigation Satellite System In 0.18μm CMOS

This dissertation presents the design and implementation of a dual band RF front end for Global Navigation Satellite System (GNSS) receivers. The dual band RF front end is composed of a pseudo differential low noise amplifier (LNA), down conversion mixers, and programmable gain amplifiers (PGA), and can be configured to operate at 1.2GHz and 1.57GHz, respectively.In this thesis, a brief introduction of CMOS navigation receiver is presented, including GNSS signal characteristics, features of sub micron CMOS process and receiver topologies. Following that, a detailed design procedure of the proposed LNA is presented. The pseudo differential LNA incorporates an active single ended to differential conversion using capacitive coupling compensation for improved phase and amplitude imbalance. A constant gm biasing circuit is used to maintain a relative constant gain over process, voltage and temperature variations. Besides, the operation frequency of this LNA can be easily configured at two frequency bands to receive different navigation signals.The down conversion mixer is based on Gilbert topology. Current bleeding technique is adopted to reduce noise and improve linearity. The high linearity PGA has a tunable gain range of 18dB with a 6dB gain step and a 0.2dB gain ripple across 30MHz bandwidth.The RF front end is implemented in SMIC 0.18 m CMOS process, occupying a die area of 1.0×0.5mm~2. The chip is directly bonded on the test PCB. Measurement results show the proposed RF front end achieves a maximum voltage gain of 68dB/66dB, a noise figure (NF) of 2.4dB/2.6dB, and an input referred 1dB compression point of–42dBm/–39dBm at 1.2GHz/1.57GHz band. The receiver front end draws 10.0mA current from a 1.8V power supply. The proposed RF front end features in less off chip components, lower NF, and larger gain control range, compared with several state of the art receivers reported in top journals and/or conferences.