The Research Of Low-power Testing Method Based On Scan Structure

With the development of integrated circuit manufacturing technology, as well as the nano-era's coming, the test power consumption is being considered as an important factor for doing IC design. Using the DFT methods based on scan structure in IC, can improve the test coverage and shorten the test time, which has been a large numbers of IC testing applications. This article analyzes the basic principles of scanning test and testing process, and also advances the effective optimization program of static and dynamic power consumption during the process of scan test.First, the scanning technology to test is analyzed comprehensively. We introduced four types of scanning cell modules: MUX-based, clock-type-specific, level-sensitive, clock-auxiliary-type. We define a new power consumption classification scheme, which has resulted in greater clarity, and more detailed type of power analysis. The focus of this paper is to offer a test new dynamic power and static power optimization methodology.In the analysis of dynamic power optimization, we propose two methods: Constant Value and Voltage Control. In the Constant Value Way, we design a new flip-flop structure, which can lock the output of flip-flop connected with the combinational logics to"0"or"1". We realize it with the logic gates operable to increase the program, which can easily control the useless transition of combinational logics. Through the experimental stage in the ISCAS89 base, we get that the test power is reduced nearly 23 % after optimization.In the Voltage Control way, we control the voltage supply of the first level combinational logics connected to flip-flops with an added gating transistor, which can also prevent the scan test signal propagating. Compared with the Constant Value way, it not only has the same power optimization, but also has higher performance at delay and area increasing. Through analyzing the result of experiment at ISCAS89, the Voltage Control way has 62% and 94% improvement at delay and area.The optimization of static power consumption is based mainly on the use of power-gating cells. The article associates the power-gating units and DFT bravely, creates a new flip-flop unit and points out a new clock distribution methods. Meanwhile we support a new method of power network production. Through an experiment of a single module design in a general-purpose high-performance microprocessor, we implement the scheme in practical design. The experimental results show that the decrease of total test power consumption is about 45% , and the total shift power consumption is reduced nearly 73%. As the significant reduction in static power consumption, useless dynamic power consumption is reduced about 92%.Finally, we sum up the main design ideas and innovations. In addition, the conclusion gives the further research and improvements to the new challenges.