Research And Implement On Resample And Synchronization Technique Of The Digital If Receiver

With the rapid development of wireless communication technology, software radio technology, computer technology and large-scale integrated circuit technology,IF digital receiver has become an important part in modern communication systems for the characteristics of generality,openness and programmable. Therefore, it is significant to research into and develop digital IF receiver. PCM/FM is used popularly in the telemetry system, With the wide development of telemetry system, the data size has to be measured is more larger, and the distance of telemetry system becomes more longer. So the noise in telemetry system is more larger,So the telemetry digital IF receiver should have good performance at low SNR(Signal Noise Ratio).In the paper resample and bit synchronization and frame synchronization technique is analyzed based on the PCM-FM telemetry digital IF receiver. The resample technique is realized by Lagrange interpolation method, and a bit synchronization algorithm at low SNR is proposed, then the optimum synchronization codeis used as the synchronization code of continuous inserting frame synchronization.What's more, a novel bit synchronization method for low SNR is suggested in this paper. Bit synchronization is known as symbol synchronization which is the special technique in communication system. Bit synchronization is needed in both baseband transmission and RF transmission system. A non-optimal bit synchronization algorithm will effect the performance of the communication system, Even caused the communication system invalid. So bit synchronization is the crucial technique of the communication system.As the SNR in PCM-FM telemetry system is lower than other common communication system, And traditional bit synchronization algorithm can't meet the requirement.So by means of mean filtering ,A bit synchronization for low SNR algorithm based on FPGA is proposed and applied to Telemetry digital IF Receiver in this paper. And via computer simulations it is shown that this algorithm has a good performance for low SNRFinally, Via the simulation with MATLAB and programming with VHDL language , and then it is compiled in the Quartus II software,running timing simulation testing and debugging with SignalTap II software. The resample and bit synchronization and frame synchronization technique is implemented on FPGA and applied to Telemetry digital IF Receiver in this paper.