Research On Space Infrared Small Target Detection And Tracking

With the development of the precision guided munition and satellite technology, the space-faring nations are increasingly concerned about the capability of space defense. Among the area the infrared small target detection and tracking plays an imperative role as a core technology of satellite remote sensing, space defense early warning and space-guided area, which is developing drametically on rapid response and long-range early warning. This thesis researches the algorithm of space infrared small target detection and tracking. In order to conquer defects the traditional software simulation always has, such as the poor real time and the weak application, the design of the algorithm based on FPGA is accomplished by DSP Builder and SOPC, which is realized on the hardware platform.Firstly, the characteristic and model of infrared small targets is analyzed. Then the algorithms relative to the target detection and tracking including image preprocessing (using medial filter and morphological filter), target detection (using threshold segmentation and Blob connexity analyzing) and target tracking (using Kalman filter) are introduced. Furthermore, software simulation is made to validate the algorithm. Secondly, the designing procedure of DSP Builder is introduced and the realization of image preprocessing, threshold segmentation and target tracking are specified in details. Thirdly, the hardware platform is selected to run the whole system. SOPC has also been used in the system with the function of image memory and result export. Finally, two kinds of source image sequences are designed including the synthesizing image based on real infrared space image and Vega emulational scene of moving infrared target. For the verification, the experiment is conducted on the hardware platform to analyze the efficiency and validity of the system.Based on the research of algorithms of infrared moving small target detection and tracking in space, this thesis finalizes the system designing on FPGA with DSP Builder and SOPC. Additionally, the practical debug and hardware experiment results show that the designed system meets the requirement of reliability and validity.