Performance Evaluation For Transaction Processing Applications Based On Shared-memory Multi-core Architectures

Transaction processing is important application on business servers. As Multi-coreprocessors are becoming common, CMPs are widely used in OLTP applications. Re-searchesaboutperformancecharacterizationaretheprimarywaypeopledesignandevalu-ate commercial multi-core system. Shared-memory MPs are widely used in current trans-action processing applications, while the performance cannot meet the demands. There-fore, how to improve performance is still an open question.Research about architectures based on shared-memory MPs need improve the archi-tectures with knowledge of characterization of transaction processing application to seekoptimum performance of multi-core platform. It needs evaluate performance of trans-action processing application, understand program behaviors and monitor utilization ofhardware and software resources. Performance evaluation is also introduced in objec-tive architecture evaluation. We can get some valuable suggestions and conclusions fromperformance evaluation for architectures optimization.This paper analyzes the performance characterization of transaction processing ap-plication with an architecture simulator based on different architecture parameters. Weanalyzed effects of L2 cache size and L2 cache association to performance of transactionprocessing application, and how cache coherence protocol and topology of CPUs influentsystem performance.This paper research system-level performance characterization of transaction pro-cessing application with hardware counter based tools. Through the system-level perfor-manceevaluation, wedividetransactionprocessingapplicationintothreephasesbasedonthe number of concurrent users, and analyze performance bottleneck of shared-memoryMP architecture in each phase.Because of the speed restriction of architecture simulator, this paper proposes ac-celerating method based on mathematic sampling and concurrent execution. With themethod, we can achieve idea simulation speed with acceptable precision-loss.