The High Speed Interfaces' Design And Realiazation Of A 10G-NP Chip

With the network and communication technology's deveopping and improving, intertnet transmission rate and network equipment's complexity is also improving. T- he proposing of Three Network Convergence policy makes it hot to research and des- ign Network Processing chip (NP-chip).The content of this paper is about a 10G Network Processing chip. In this paper I will describe the realization and design of the interface part of this chip. The interface part include media access control sublayer(MAC),interfaces beween MAC and the o- ther part inside the chip. The design of this chip uses a top-down method. With the st- udying of 802.3 Ethernet MAC protocol and the requirements of the project, I compl- eted the modules'dvising, at last realize the circuit's design. This chip is part of the P- TN network equipment, it can work under the concentration mode and the distributed mode. When the chip was used under the distributed mode, all the interfaces can be u- sed 100%. When the chip was used under the concentration mode, there can be 20G data flow pass through the MAC interfaces, but there is only 10G data flow can be tr- ansfered through the chip, so we introduce a dataflow control strategy. The dataflow control strategy was realized by using a token bucket based on the service level. Coo- rdinating with the software design, the chip's flow control function can be adaptive.