FPGA Network Development Platform Hardware Software Co-design And Co-verification

Network development platform is a framework that can be used to develop new network applications. The framework includes essential network data processing modules and supporting modules used for network application development. Platform allows user to build their system prototype faster, evaluate system's performance earlier and shorten the design cycle. First, this article analyzes current research activities on network development platform. Than, based on FPGA architecture, we analysis system framework and requirements, define its interface signals, data format, and finally built a network development platform. System's user expansion interface can provide gigabit wire-speed rate network data, so users do not have to care about concrete realization of underlying network protocol and can only focus on data processing. System also provides abundant reusable verification tasks that can be used to accelerate user's validation process.Focus on the key points, this paper describes registers'functionality and organization that added to the PCI protocol module. This paper also describes the detailed implementation of Ethernet protocol and SRAM's store structure, and gives out the corresponding FSM and state transition table. This paper also describes the specific user interface signals and data format, provides user a good second development interface. In addition, for the problem that asynchronous signal may produce metastable and impact system stability, we propose an improved Cascade triggers edge detection method, designed an asynchronous signal processing module to solute the defect that cascade triggers can only detect pulse's rising edge or falling edge and can not detect a continuous signal.This paper introduce software and hardware Co-design and co-verification methods in the FPGA network development platform design process to shorten the time of design implementation. When validating the platform, we use direct vector test and the random excitation vector data test method to provide test data.System use a hierarchical verification method: module-level verification is carried out simultaneously with system level verification and done by module designer. It ensures module's logic is correct and meets system's timing requirements after synthesize. Interface-level verification include verifying PCI protocol and IEEE 802.3 Ethernet protocol, each protocol is designed to meet platform's requirements and corresponding protocol specification. System-level verification uses platform's reusable verification modules supporting missions to provide system inputs, and checks input and output data's integrity.From systematic aspect, this paper analysis network develop platform's FPGA logic design and verification needs, module partition, signals definition of modules and interfaces; then, using verilog-HDL to implement FPGA-based network develop environment, and verified its overall function. Finally, as a secondary development example, we design traffic data collection module based on network development environment, and validate the platform can work in Gigabit network.